1. Field of the Invention
The present invention relates to improvements in cascode configurations. More particularly, the invention relates to improvements particularly suited for high temperature circuit environments requiring low noise and precise control.
2. Description of the Known Art
In high temperature environments, SiC JFETs have favorable characteristics. The simple JFET structure does not require a metal oxide layer at the gate so it is an attractive switch for high temperature applications. The two commercially available options, E-mode and D-mode SiC JFETs have different advantages and disadvantages for power electronics. D-Mode JFETs generally offer lower ON state resistance than similarly rated E-mode JFETS. However, D-mode JFETS are normally ON and this provides a disadvantage during power loss in the control modules. The E-Mode JFETs are the opposite with a normally OFF state, but present a higher ON state resistance than the D-Mode JFET. Additionally, the E-Mode devices also have a relatively low operational voltage range (approximately 3.5V) between the gate and source. This lower operational voltage translates into a lower signal to noise ratio that increases the possibility of power-switching noise corrupting the gate signal.
FIGS. 1 and 2 show prior art SiC JFET based switch positions under a clamp-inductive test setup. FIG. 1 shows a prior art Lone D-mode JFET switch position. It is known in the prior art how to use and drive a D-Mode JFET in this configuration. FIG. 2 shows a traditional cascode arrangement using an SiC D-mode JFET with an E-Mode JFET. Note how it is known to generate and provide a gate signal to the E-mode JFET but to then tie the gate of the D-Mode JFET to ground. This type of SiC cascode combines the high voltage blocking D-Mode SiC JFET with the normally-off characteristics of the E-Mode JFET to yield a high voltage normally-off power switch. However, this arrangement suffers from noise susceptibility at the gate and high voltage ringing at the gate terminal.
As will be appreciated by those skilled in the art, cascode circuits are known in various forms. Patents disclosing information relevant to cascode circuits include: U.S. Pat. No. 7,719,055 issued to McNutt, et al. on May 18, 2010 entitled Cascode Power Switch Topologies; U.S. Pat. No. 7,782,118, issued to Reichl, et al. on Aug. 24, 2010 entitled Gate Drive for Wide Bandgap Semiconductor Device; U.S. Pat. No. 6,614,281, issued to Baudelot, et al. on Sep. 2, 2003 entitled Method and Device for Disconnecting a Cascode Circuit with Voltage-Controlled Semiconductor Switches. Each of these patents is hereby incorporated by reference in their entirety. These patents fail to teach the advantages, method, or apparatus of the present invention.
U.S. Pat. No. 7,719,055 issued to McNutt, et al. on May 18, 2010 is entitled Cascode Power Switch Topologies. Its abstract reads as follows: A normally-off cascode power switch circuit is disclosed fabricated in wide bandgap semiconductor material such as silicon carbide or gallium nitride and which is capable of conducting current in the forward and reverse direction under the influence of a positive gate bias. The switch includes cascoded junction field effect transistors (JFETs) that enable increased gain, and hence blocking voltage, while minimizing specific on-resistance.
U.S. Pat. No. 7,782,118, issued to Reichl, et al. on Aug. 24, 2010 is entitled Gate Drive for Wide Bandgap Semiconductor Device. The abstract reads as follows: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor. The gate drive circuitry provides a small, efficient, and cost effective control circuitry for a wide bandgap semiconductor junction gated transistor.
U.S. Pat. No. 6,614,281, issued to Baudelot, et al. on Sep. 2, 2003 entitled Method and Device for Disconnecting a Cascode Circuit with Voltage-Controlled Semiconductor Switches. The abstract reads as follows: A method and an apparatus for turning off a cascode circuit comprising a series circuit formed by a low-blocking-capability and high-blocking-capability semiconductor switch, are described. When a turn-off command arrives, the gate voltage of the low-blocking-capability semiconductor switch is controlled in such a way that its drain voltage is held constant in the active range of the low-blocking-capability semiconductor switch. Consequently, an impermissible overvoltage at high potential of the cascode circuit at low potential is detected and actively limited. Each of these patents is hereby expressly incorporated by reference in their entirety.
From these prior references it may be seen that these prior art patents are very limited in their teaching and utilization, and an improved Normally-Off Direct Drive Cascode is needed to overcome these limitations.